library ieee;
use ieee.std_logic_1164.all;

--I0 will be the output if S is 0
--I1 will be the output if S is 1
entity mux2to1 is
	port (I0, I1, S : in bit;
        F : out bit);
end entity mux2to1;

architecture DATAFLOW of mux2to1 is
    
    signal andOut : bit_vector(1 downto 0);
    
    begin
        
        andOut(0) <= I0 and (not S);
        andOut(1) <= I1 and S;
        
       	F <= andOut(0) or andOut(1);
		
end architecture DATAFLOW;